1. Field of the Invention
The present invention generally relates to plasma display apparatuses, and particularly relates to a plasma display apparatus that has an improved display quality.
2. Description of the Related Art
Plasma display panels have two glass plates on which electrodes are formed, and discharge-purpose gas fills the gap between the two glass plates that is in the order of 100 microns. Voltages higher than a discharge threshold voltage are applied between the electrodes to start gas discharge, and ultraviolet light generated from the discharge induces the light emission of photo florescent provided on the plate, thereby effecting screen displaying.
FIG. 1 is a diagram showing a schematic configuration of a plasma display apparatus.
A display panel 10 includes X electrodes 11 and Y electrodes 12 disposed in parallel, and further includes address electrodes 13 disposed in perpendicular thereto. The X electrodes 11 and the Y electrodes 12 are used to provide sustain discharge for display-purpose light emission. Voltage pulses are applied between the X electrodes 11 and the Y electrodes 12, thereby carrying out sustain discharge. Further, the Y electrodes 12 serve as scan-purpose electrodes for writing display data. The address electrodes 13 are used to select display cells 15 that are to emit light. A voltage for writing discharge is applied between the Y electrodes 12 and the address electrodes 13 so as to select discharge cells. Shields 14 are provided between the address electrodes 13 for the purpose of separating the discharge cells 15.
Discharge of a plasma display panel can only assume either one of the xe2x80x9conxe2x80x9d state and the xe2x80x9coffxe2x80x9d state, so that the density, i.e., the gray scale, is represented by the number of repeated light emissions. To this end, a frame is divided into 10 sub-fields, for example. Each sub-field is comprised of a reset period, an address period, and a sustain discharge period. During the reset period, all cells are equally initialized regardless of lighting status in the previous sub-fields, e.g., are placed in the condition in which wall charge is erased. During the address period, selective discharge (addressing discharge) is performed to select the on/off states of cells in accordance with display data, thereby selectively generating wall charge that places cells in the xe2x80x9conxe2x80x9d state. During the sustain discharge period, discharge is repeated in the cells where addressing discharge was performed to generate wall discharge, thereby emitting light. The length of the sustain discharge period, i.e., the number of repeated light emissions, differs from sub-field to sub-field. For example, ratios of the numbers of light emissions from the first sub-field to the tenth sub-field are set to 1:2:4:8: . . . :512, respectively. Sub-fields are then selected in accordance with the luminance level of a display cell to be subjected to gas discharge, thereby achieving a desired gray scale level.
FIG. 2 is a drawing showing another configuration of a display panel unit different from that of FIG. 1.
In a display panel unit 10A of FIG. 2, X electrodes 11A and Y electrodes 12A serving as display electrodes are provided in turn at equal intervals so as to cross address electrodes 13A. All gaps between the electrodes are utilized as display lines (L1, L2, . . . ). This configuration is called an ALIS (alternate lightning of surfaces) method, and is disclosed in Japanese Patent No. 2801893. Since all the gaps between the electrodes are utilized as display lines, the number of electrodes is half as many as that of FIG. 2, which provides a basis for a cost reduction and a scale reduction.
Since all the gaps between electrodes serve as display lines in the ALIS method, it is impossible to light up all the display lines simultaneously. Lighting of odd-number lines (L1, L3, . . . ) and even-number lines (L2, L4, . . . ) are temporally separated to effect displaying. In the ALIS method, One frame is divided into two fields, each of which is comprised of a plurality of sub-fields. The first field is used for the displaying of odd-number lines, and the second field is used for the displaying of even-number lines.
FIG. 3 is a drawing showing a configuration of a related-art plasma display apparatus.
The plasma display apparatus of FIG. 3 includes a plasma display panel 20, a Y electrode drive circuit 21, an X electrode drive circuit 22, an address electrode drive circuit 23, a discrimination decision circuit 24, a memory 25, a control circuit 26, and a scanning circuit 27.
A vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a clock signal Clock, and RGB signals each comprised of 8 bits and serving as data signals are supplied to the discrimination decision circuit 24. The discrimination decision circuit 24 writes RGB data in the memory 25 as display data in response to the vertical synchronizing signal Vsync. The control circuit 26 controls the Y electrode drive circuit 21, the X electrode drive circuit 22, the address electrode drive circuit 23, and the scanning circuit 27, and displays the display data stored in the memory 25 on the plasma display panel 20. In conjunction with this, the scanning circuit 27 scans the Y electrodes Y1 through Yn, and the address electrode drive circuit 23 drives the address electrodes A1 through An, thereby together effecting writing electric discharge for writing data in the plasma display panel 20. In the display cells where data were written, further, sustain electric discharge is generated between the Y electrodes Y1 through Yn and the X electrodes X1 through Xn by the Y electrode drive circuit 21 and the X electrode drive circuit 22.
In the related-art configuration shown in FIG. 3, lines y1 through yn that extends from the Y electrode drive circuit 21 to the scanning circuit 27 to be connected to the Y electrodes Y1 through Yn take different wiring paths between the Y electrode drive circuit 21 and the scanning circuit 27, so that they have different wire lengths. In the example of FIG. 3, similarly, the X electrodes X1 through Xn extending from the X electrode drive circuit 22 to the plasma display panel 20 take different wiring paths to have different wire lengths. The line y1 and the Y electrode Y1 connected thereto both having long wiring lengths have wiring resistance and wiring inductance larger than those of the line y3 and the Y electrode Y3 connected thereto both having relatively short wiring lengths. By the same token, the X electrode X1 having a long wiring length has wiring resistance and wiring inductance larger than those of the X electrode X3 having a relatively short wiring length. An effect of the wiring inductance is especially strong. Because of this, when an electric current runs through wiring lines and electrodes to generate electric discharge between the Y electrodes Y1 through Yn and the X electrodes X1 through Xn, a voltage drop occurs along the wiring lines and electrodes. The voltage drop generated in this manner differs from wiring line to wiring line and from electrode to electrode.
As a result of this voltage drop, when a sufficient margin cannot be secured for the discharge voltage of a plasma display panel with respect to the electrodes having a large voltage drop, a sufficient voltage required to light up an electric discharge may not be supplied. In such a case, a flicker of a screen or the like will appear, thereby degrading display quality.
Accordingly, the present invention is aimed at providing a plasma display panel in which a voltage drop produced in accordance with a wire length is reduced. Moreover, the present invention is aimed at providing a plasma display panel in which a variation in voltage drops produced according to wire lengths is reduced, thereby improving the quality of images.
It is a general object of the present invention to provide a plasma display apparatus that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
In order to achieve the above objects according to the present invention, a plasma display apparatus includes a plurality of first electrodes, a plurality of second electrodes which are arranged in substantially parallel to the plurality of first electrodes and generate electric discharge with the plurality of first electrodes at gaps therebetween, a first drive circuit which applies an electric discharge voltage to the plurality of first electrodes, a second drive circuit which applies an electric discharge voltage to the plurality of second electrodes, and voltage fluctuation balancing units which are provided for wiring lines between the first and second drive circuits and the first and second electrodes, and each of which has a conductive plate layer overlapping at least part of the wiring lines so as to reduce a variation in voltage drops specific to the wiring lines by eddy currents generated in the conductive plate layer in response to currents running through the wiring lines.
Alternatively, the voltage fluctuation balancing units each include a reverse current line laid out along one of the wiring lines and having a current running therethrough in a direction opposite to a current running through the one of the wiring lines so as to reduce a variation in voltage drops specific to the wiring lines.
Alternatively, the voltage fluctuation balancing units each apply a voltage to at least one of the wiring lines where the applied voltage has an identical polarity to a voltage applied to the at least one of the wiring lines, thereby reducing a variation in voltage drops specific to the wiring lines.
The configurations as described above provide a plasma display panel apparatus in which a variation in voltage drops produced in accordance with wire lengths is reduced, thereby improving the quality of images.
According to another aspect of the present invention, a plasma display apparatus includes a plurality of first electrodes, a plurality of second electrodes which are arranged in substantially parallel to the plurality of first electrodes and generate electric discharge with the plurality of first electrodes at gaps therebetween, a first drive circuit which applies an electric discharge voltage to odd-number electrodes of the plurality of first electrodes, and a second drive circuit which applies an electric discharge voltage to even-number electrodes of the plurality of first electrodes, wherein the first drive circuit and the second drive circuit have a mutually symmetrical input/output pin arrangement.
Such s symmetrical pin arrangement makes it possible to lay out wiring lines in a balanced arrangement, thereby efficiently reducing voltage drops caused by the wiring inductance and balancing the voltage drops.
According to another aspect of the present invention, a plasma display apparatus includes a plurality of first electrodes, a plurality of second electrodes which are arranged in substantially parallel to the plurality of first electrodes and generate electric discharge with the plurality of first electrodes at gaps therebetween, a first integrated circuit which includes a high-side odd-number electrode drive circuit for supplying a high voltage to odd-number electrodes of the first electrodes and a low-side even-number electrode drive circuit for supplying a low voltage to even-number electrodes of the first electrodes, and a second integrated circuit which includes a low-side odd-number electrode drive circuit for supplying a low voltage to the odd-number electrodes of the first electrodes and a high-side even-number electrode drive circuit for supplying a high voltage to the even-number electrodes of the first electrodes.
In the invention described above, each electrode drive circuit is divided into an H-side circuitry and an L-side circuitry, and electrode drive circuits and wiring lines are arranged such that currents run in opposite directions between adjacent wiring lines at each electric discharge timing. This makes it possible to cut down the influence of wiring inductance.
According to another aspect of the present invention, a plasma display apparatus, which includes a plurality of first electrodes and a plurality of second electrodes that are arranged in substantially parallel to the plurality of first electrodes and generate electric discharge with the plurality of first electrodes at gaps therebetween, includes a plurality of blocks into which the plurality of first electrodes are divided, wherein each block is provided with an odd-number electrode drive circuit for driving odd-number electrodes of the first electrodes and an even-number electrode drive circuit for driving even-number electrodes of the first electrodes.
In the invention described above, each electrode drive circuit is divided into a plurality of circuitries, and electrode drive circuits and wiring lines are arranged such that currents run in opposite directions between adjacent wiring lines at each electric discharge timing. This makes it possible to cut down the influence of wiring inductance.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.